| Properties | |
|---|---|
| bits2AdministrativeState | applicable=false |
| bits2Alarms | applicable=false |
| bits2InUse | applicable=false |
| bits2InputState | applicable=false |
| bits2OutputState | applicable=false |
| bits2Qualified | applicable=false |
| bits2State | applicable=false |
| bits2TimingReferenceRxQltyLevel | applicable=false |
| bits2TimingReferenceTxQltyLevel | applicable=false |
| bitsAdministrativeState | applicable=false |
| bitsAlarms | applicable=false |
| bitsInUse | applicable=false |
| bitsInterfaceType | applicable=false |
| bitsOutQlMinimum | applicable=false |
| bitsOutSquelch | applicable=false |
| bitsOutputRefSel | applicable=false |
| bitsOutputState | applicable=false |
| bitsQualified | applicable=false |
| bitsQualityLevel | applicable=false |
| bitsSource | applicable=false |
| bitsState | applicable=false |
| bitsTimingReferenceRxQltyLevel | applicable=false |
| bitsTimingReferenceTxQltyLevel | applicable=false |
| bitslineLength | applicable=false |
| externalInIfAdminStatus | applicable=false |
| externalInIfType | applicable=false |
| externalInTimingReferenceAlarms | applicable=false |
| externalInTimingReferenceInUse | applicable=false |
| externalInTimingReferenceQualified | applicable=false |
| externalInTimingReferenceQualityLevel | applicable=false |
| externalInTimingReferenceState | applicable=false |
| externalInputImpedanceType | applicable=false |
| externalOutIfType | applicable=false |
| fifthTimingReferenceInput | applicable=false |
| firstTimingRefBitsInterfaceType | applicable=false |
| firstTimingReferenceAdministrativeState | write-access=no (from 6.1.R1) |
| firstTimingReferenceInput |
suppress enums=bits1, bits2, external, synce, gnss write-access=no (from 6.1.R1) |
| firstTimingReferenceInterfaceName | applicable=false |
| firstTimingReferenceInterfacePointer | applicable=false |
| firstTimingReferencePortName | write-access=no (from 6.1.R1) |
| firstTimingReferencePortPointer | write-access=no (from 6.1.R1) |
| firstTimingReferenceQualityLevel | supported from=8.0.R4 |
| firstTimingReferenceRxQltyLevel | supported from=8.0.R4 |
| firstTimingReferenceSaBit |
supported from=8.0.R4 excluded chassis types=7750-SR12-MG, 7750-SR7-MG, VSR-MG |
| firstTimingReferenceSourceBit | applicable=false |
| firstTimingReferenceSourceBitPointer | applicable=false |
| firstTimingReferenceSrcPtpClock | applicable=false |
| firstTimingReferenceState | supported from=8.0.R1 |
| firstTimingReferenceType | applicable=false |
| fourthTimingReferenceInput | applicable=false |
| gnssAdminStatus | applicable=false |
| gnssAlarms | applicable=false |
| gnssInUse | applicable=false |
| gnssQltyLevel | applicable=false |
| gnssQualified | applicable=false |
| gnssState | applicable=false |
| gnssTimingRefRxQltyLevel | applicable=false |
| mateCPMReferenceAlarms | applicable=false |
| mateCPMReferenceInUse | applicable=false |
| mateCPMReferenceQualified | applicable=false |
| mateCPMReferenceState | applicable=false |
| minQualityLevel | applicable=false |
| primaryTimingReferenceType | applicable=false |
| ptpAdministrativeState | applicable=false |
| ptpAlarms | applicable=false |
| ptpInUse | applicable=false |
| ptpQualified | applicable=false |
| ptpQualityLevel | applicable=false |
| ptpState | applicable=false |
| ptpTimingReferenceRxQltyLevel | applicable=false |
| qualityLevel | supported from=8.0.R4 |
| revertive | write-access=no (from 6.1.R1) |
| saBit | applicable=false |
| secondTimingRefBitsInterfaceType | applicable=false |
| secondTimingReferenceAdministrativeState | write-access=no (from 6.1.R1) |
| secondTimingReferenceInput |
suppress enums=bits1, bits2, external, synce, gnss write-access=no (from 6.1.R1) |
| secondTimingReferenceInterfaceName | applicable=false |
| secondTimingReferenceInterfacePointer | applicable=false |
| secondTimingReferencePortName | write-access=no (from 6.1.R1) |
| secondTimingReferencePortPointer | write-access=no (from 6.1.R1) |
| secondTimingReferenceQualityLevel | supported from=8.0.R4 |
| secondTimingReferenceRxQltyLevel | supported from=8.0.R4 |
| secondTimingReferenceSaBit |
supported from=8.0.R4 excluded chassis types=7750-SR12-MG, 7750-SR7-MG, VSR-MG |
| secondTimingReferenceSourceBit | applicable=false |
| secondTimingReferenceSourceBitPointer | applicable=false |
| secondTimingReferenceSrcPtpClock | applicable=false |
| secondTimingReferenceState | supported from=8.0.R1 |
| secondTimingReferenceType | applicable=false |
| secondaryTimingReferenceType | applicable=false |
| syncE2Alarms | applicable=false |
| syncEAdministrativeState | applicable=false |
| syncEAlarms | applicable=false |
| syncEInUse | applicable=false |
| syncEQualified | applicable=false |
| syncEQualityLevel | applicable=false |
| syncEState | applicable=false |
| syncETimingReferenceRxQltyLevel | applicable=false |
| systemQualityLevel | supported from=8.0.R4 |
| thirdTimingReferenceInput |
excluded chassis types=7750-SRc12, 7450-ESS6, 7450-ESS1, 7450-ESS6V suppress enums=bits1, bits2, external, synce, gnss write-access=no (from 6.1.R1) |
| waitToRestore | applicable=false |